Completely acceptable as a clever hack, or for real production designs?
It's the explicit purpose of the submodule. It's like a microprocessor with fine-grained clockspeed control (fraction of the main CPU clock) and like 9 instructions that focus on driving GPIO pins. There's FIFO queues for pushing/pulling data from/to the PIO from/to the main CPU, so you don't have to waste any real clock cycles (other than to make sure your buffers aren't starved)
> (fraction of the main CPU clock)
Just watch out for aliasing jitter at higher fractions (frequencies). If that's going to be an issue, it's best to use integer fractions of the main CPU clock, if possible.
Yeah, that's definitely a concern! The datasheets gives an example of serial communication and recommends using non-standard baud-rates to avoid this problem. It's not perfect, but my point was it's not just another MCU, there is actually some hardware that makes it somewhat unique.
You can also adjust the system clock if you're desperate, though I'm not sure if that would entirely eliminate jitter (I haven't tried it)
Have you actually used one or looked at the datasheet? The 4 PIO state machines are pretty unique in the MCU ecosystem as far as I can tell. It makes "bitbanging" a completely acceptable approach for a huge number of protocols.