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> (fraction of the main CPU clock)

Just watch out for aliasing jitter at higher fractions (frequencies). If that's going to be an issue, it's best to use integer fractions of the main CPU clock, if possible.


packetlost
Yeah, that's definitely a concern! The datasheets gives an example of serial communication and recommends using non-standard baud-rates to avoid this problem. It's not perfect, but my point was it's not just another MCU, there is actually some hardware that makes it somewhat unique.

You can also adjust the system clock if you're desperate, though I'm not sure if that would entirely eliminate jitter (I haven't tried it)

vardump OP
FPGAs definitely do have their place with their nice (fractional) PLLs and separate clock domains when it comes to applications like these.

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