Aging, thermal cycling, signal emissions, signal corruption, reliability, testability, failure dynamics, and a hundred other manufacturing, maintenance, usability, and reliability profiles are subtly affected by placement and layout that one learns to intuit over the years.
I’m not saying that AI can’t capture that eventually, but I am saying that just following simple heuristics and ensuring DRC compliance only gets you 80 percent of the way there.
There is as much work in getting the next 15 percent as there was in the first 80, and often requires a clean slate if the subtleties weren’t properly anticipated in the first pass. The same stands for the next 4 percent. The last 1 percent is a unicorn. You’re always left with avoidable compromises.
For simple stuff where there is plenty of room, you can get great results with automation. For complex and dense elements, automation is very useful but is a tool wielded with caution in the context of a carefully considered strategy in emc, thermal, and signal integrity trade offs. When ther is strong cost pressure it adds a confounding element at every step as well.
In short, yes, it will boot. No, it will not be as performant when longevity, speed, cost, and reliability is exhaustively characterized. Eventually it may be possible to use AI to produce an equivalent product, but until we have an exhaustive training set of “golden boards” and their schematics to use as a training set, it will continue to require significant human intervention.
Unfortunately, well routed, complex boards are typically coveted and carefully guarded IP, and most of the the stuff that is significantly complex yet freely and openly available in the wild is still in the first 80percent, if even. The majority of circuit boards in the wild are either sub-optimally engineered or are under so much cost pressure that everything else is bent to fit that lens. Neither one of those categories make good training data, even if you could get the gerbers.
The only reason people usually route PCBs is that defining the constraints for an autorouter is generally more work than just manually routing a small PCB, but within semiconductors autorouting overtook manual routing decades ago.
i guess maybe there are less degrees of freedom and more 'regularity' in the semiconductor space? sort of like a fish swimming in an amorphous ocean vs. having to navigate uneven terrain with legs and feet. the fish in some sense is operating in a much more 'elegant' space, and that is reflected in the (beautiful?) simplicity of fish vs. all the weird 'nonlinear' appendages sticking out of terrestrial animals - the guys who walk are facing a more complicated problem space.
i guess with pcbs you have 'weird' or annoying constraints like package dimensions, via size, hole size, trace thickness, limited layer count, etc.
With PCB its all still quite manageable, even something like whole PC motherboard is easily doable by two-three EEs specializing in different niches (power, thermals, high speed digital design).