> Single cycle readings defeat the point of sigma delta ADC setups.
The ADC's internal delta-sigma ADC takes a lot of samples at a much higher modulation frequency and presents them as a single output value.
You do not get the direct delta-sigma output from an ADC like this. The internal logic handles that for you. It's okay to take single samples of the output.
OP is using the chip with the data rate set to 8 samples per second.
Natively/internally, it runs at 860 samples per second, and you can configure it to provide that data at a lower sample rate at lower noise levels by averaging multiple readings together internally.
Single cycle readings defeat the point of sigma delta ADC setups.
You're taking many high noise samples and averaging them over time to get a better picture of the average voltage.