>This would strip out tons of MOV instructions which was proven with AMD64 to have a decent impact on performance.
Sure, but the topic is optimizing power efficiency by removing support for an instruction set. That aside, if an instruction isn't very performant, it isn't much of an issue per se. It just means it won't get used much and so chip design resources will be suboptimally allocated. That's a problem for Intel and AMD, and for nobody else.
rerdavies
ARM has THREE instruction sets. (four?) aarch32, aarch64, and various incarnations of Thumb. (A PI 5 supports all three).
fluoridationOP
Okay? x86-64 has like twenty extensions. What's your point?
rerdavies
The point was that, with respect to the effects of implementing multiple decode stages for multiple instruction sets, ARM doesn't have an advantage over x86 in that respect.
(M1 does, because they don't implement aarch32, or thumb).
Sure, but the topic is optimizing power efficiency by removing support for an instruction set. That aside, if an instruction isn't very performant, it isn't much of an issue per se. It just means it won't get used much and so chip design resources will be suboptimally allocated. That's a problem for Intel and AMD, and for nobody else.