If you look at the XC2064 datasheet[1], you'll see there are 12,038 configuration bits, only 1024 of those bits actually program the LUTs, and 90% are for routing. For general purpose logic replacement, that offers great flexibility.

If you want to do general purpose computing, it's my strong (and minority) opinion that routing fabrics are a premature optimization. The trend has been in the wrong direction.

If you were to go the other way, and just build a systolic array of look up tables, as I have hypothesized for years with my BitGrid, you could save 90% of the silicon, and still get almost all of the compute. It gets better when you consider the active logic would only be between neighboring cells, thus capacitive power would be much lower, and speeds could be higher.

[1] https://downloads.reactivemicro.com/Electronics/FPGA/Xilinx%...