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vardump parent
It's interesting how arbitrarily CPU bitness is defined. Sometimes it's the register size, sometimes data bus width and sometimes the address width.

6502 has 8 bit registers, 8 bits wide data bus, and 16 bit addresses. Only PC register is 16-bit, but 6502 does have a zero page indirect 16-bit addressing mode.


wang_li
Sometimes by register size, sometimes by ALU size, sometimes by data bus width. But I've never heard of a CPU bitness defined by address bus size.

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