Wouldn't it be funny to see that CPU produced on a modern node?
Given the low transistor count, you could probably achieve speeds in the multi-10s of GHz, it would be so small.
A multi-core 99/4A would be hilarious to witness.
kragen
With MESI cache coherence, maybe you could migrate the whole workspace for your subroutine into a line of your core's L1D cache, and make it perform like hardware registers while retaining the pleasantly parsimonious TMS 990 architectural semantics?
Given the low transistor count, you could probably achieve speeds in the multi-10s of GHz, it would be so small.
A multi-core 99/4A would be hilarious to witness.