_sbrk parent
It's not just that the boards are expensive; you'll also need a Vivado license to create any designs for it. That license is at least several thousand dollars for the Versal devices.
It's taken many years of reverse engineering, but there's now an efficient OSS toolchain for the smaller Artix7 FPGA family, https://antmicro.com/blog/2020/05/multicore-vex-in-litex/
Artix 7 is simplistic compared to any of the Versal chips. You buy an expensive FPGA and then try using an "open-source" tool chain that exposes 25% of the FPGA's potential. Not a great trade-off, eh?
This blog doesn't seem to talk about the OSS toolchain, litex/vexriscv are very neat but they don't replace Vivado, right?
Like all open-source, it's an ongoing effort. Bunnie has a comparison, https://www.bunniestudios.com/blog/2017/litex-vs-vivado-firs...
> Thanks to the extensive work of the MiSoC and LiteX crowd, there’s already IP cores for DRAM, PCI express, ethernet, video, a softcore CPU (your choice of or1k or lm32) and more.. LiteX produces a design that uses about 20% of an XC7A50 FPGA with a runtime of about 10 minutes, whereas Vivado produces a design that consumes 85% of the same FPGA with a runtime of about 30-45 minutes.. LiteX, in its current state, is probably best suited for people trained to write software who want to design hardware, rather than for people classically trained in circuit design who want a tool upgrade.
I think transpute likely meant to link F4PGA[1] or one of the projects it makes use of (Yosys, nextpnr, Project IceStorm, Project X-Ray, etc).
Thanks for the pointer! DARPA ERI investment was initially directed to US academic teams, while Yosys & related decentralized OSS efforts were barely running on conviction fumes in the OSS wilderness. Glad to see this umbrella ecosystem structure from LF Chips Alliance. Next we need a cultural step change in commercial EDA tools.