100%, all the recommendations to "start" with the FOSS toolchain are totally bogus.
"You want to learn FPGAs! Let's simulate with Verilator. No, it can't simulate delays, or your vendor's IP library. No, it's not mixed language - hope all your IP is Verilog! And you'll need to know C or C++ to write your test bench, but that's ok right? The examples online involve templates (ZipCPU), so you're OK with Makefiles, and templated C++, obviously. Now, you have the FOSS P&R tools! They use a primitive simulated annealing placement algorithm that's like what we did in the 90's. Yeah, that's terrible, but don't worry, it works fine because the only parts you can target are really, really tiny Lattice parts! No, you can't even use all the hard blocks on the 7 series Xilinx parts - you can fit ONE whole RISC-V superscalar OoO core on the $3500 VC707 (https://github.com/csail-csg/riscy-OOO), running at ~120MHz - but I'll bet you'll do some primitive microcontroller RISC-V instead, something that fits on these really, really, REALLY tiny parts. Then you'll obviously want to augment that with Migen - don't you also know Python? Or Chisel! How great is Scala right? Yeah, it couldn't simulate a simple tri-state until version 2, but you're OK with the concept of domain specific languages already, right? You love the first-class functions and code as data concept! I know, I know. No, nobody in industry cares about any of this stuff, they're too busy using actual FPGA knowledge to like build real systems and circuits. Yeah, a microcontroller-level RISC-V style processor is a handful of undergraduate labs, but RISC-V IS OPEN! Anyway, back to FPGAs...hey where are you going?!"
"You want to learn FPGAs! Let's simulate with Verilator. No, it can't simulate delays, or your vendor's IP library. No, it's not mixed language - hope all your IP is Verilog! And you'll need to know C or C++ to write your test bench, but that's ok right? The examples online involve templates (ZipCPU), so you're OK with Makefiles, and templated C++, obviously. Now, you have the FOSS P&R tools! They use a primitive simulated annealing placement algorithm that's like what we did in the 90's. Yeah, that's terrible, but don't worry, it works fine because the only parts you can target are really, really tiny Lattice parts! No, you can't even use all the hard blocks on the 7 series Xilinx parts - you can fit ONE whole RISC-V superscalar OoO core on the $3500 VC707 (https://github.com/csail-csg/riscy-OOO), running at ~120MHz - but I'll bet you'll do some primitive microcontroller RISC-V instead, something that fits on these really, really, REALLY tiny parts. Then you'll obviously want to augment that with Migen - don't you also know Python? Or Chisel! How great is Scala right? Yeah, it couldn't simulate a simple tri-state until version 2, but you're OK with the concept of domain specific languages already, right? You love the first-class functions and code as data concept! I know, I know. No, nobody in industry cares about any of this stuff, they're too busy using actual FPGA knowledge to like build real systems and circuits. Yeah, a microcontroller-level RISC-V style processor is a handful of undergraduate labs, but RISC-V IS OPEN! Anyway, back to FPGAs...hey where are you going?!"