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JosephRedfern parent
I don't think the M4 is a typo. Apparently it's based on the NXP i.MX 8M, who's block diagram definitley states Cortex-M4 w/ 16K L1 Cache: https://www.nxp.com/products/processors-and-microcontrollers....

M4 application notes (http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc....) says the M{-0..4} doesn't have any internal cache, but that it can be provided by the SoC. Presumably that's what's happening here -- although it seems weird that this can be called an L1 Cache (although I'm by no means an expert on this so can't really comment!).


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