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It seems like SMT would create considerably more cache pressure, as well as requiring more decode and instruction cache hardware. I have been assuming it actually requires more die area, and is not (always) just disabled for segmentation. Maybe there is someone here who knows more about architecture? :)

Binning.

So you do all the lithography, and vapor deposits on a wafer. That wafer has ~100 physical processors on it (100 just to make rounding easier). You split them (into individual chips), and you start testing.

Say on ~10 Hyper Threading, all the cache cells, and all the magic virtualization stuff works. These become some pro-sumer Xeon type deal.

On another ~10 Hyper Thread, and all cache cells works. This is your i9's

On another ~30 no Hyper Threading, and only some cache cells works. This is your i7's

The rest there is no Hyper Threading, only some cache cells work, and wow only 4 physical cores work. This is your i5's and i3's (kind of).

The idea is yeah, whole parts of a CPU are defective, or unperforming. So they just get disabled and "binned" as another lower tier CPU of the same micro-architecture. All of these get solid at >100-5000x markup to offset the $50bil+ in R&D Intel spends each year. Yes their margins, are... amazing.

Generally true but in practice there are almost no CPUs where the only thing that is broken is hyperthreads. All CPU companies will disable fully-functional chips to make that segment of their product lineup.

Also, the reality is that the consumer market is a massive beneficiary of this whole scheme. The server market is effectively subsidizing consumer processors to the tune of billions, if consumers had to pay full freight on their dies prices would be several times higher than they are.

    if consumers had to pay full freight on their dies prices
     would be several times higher than they are. 
This is doubtful, Intel's margins are amazing as they're fully integrated vertical monopoly. They make the wafers, own the fabs, cut their own masks, etc. Very literally sand comes in one end, and chips come out the other.

The fundamental processes of producing an equal die space SoC as a Xeon on the same (node) is likely roughly equal cost (or I imagine the fabs as a service would go out of business). So saying Intel -needs- the consumer market to subsidize their server line is a total lie.

Intel puts an extreme markup on their server class processors, and a milder mark up on the consumer segment

It's definitely there but disabled.

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